Low area architecture in BCH decoder

ABSTRACT

An improvement to a key equation solver block for a BCH decoder, where the key equation solver block having a number of multiplier units specified by X, where: t*(7*t−1)/(codeword_len−3)≦X&lt;(t+1), where t is a number of transmission errors for the key equation solver block to correct, and codeword_len is a length of a transmitted codeword to be decoded by the BCH decoder.

FIELD

This invention relates to the field of integrated circuits. More particularly, this invention relates to error correcting codes, such as those used during the transmission of digital information.

BACKGROUND

BCH (Bose-Chaudhuri-Hocquenghem) codes are a large class of multiple error-correcting codes. The binary BCH codes were discovered in 1959 by Hocquenghem and independently in 1960 by Bose and Ray-Chaudhuri. Later, Gorenstein and Zierler generalized them to all finite fields. At about the same time Reed and Solomon published their paper on the special case of BCH codes that now bear their names.

In practice, the binary BCH and Reed-Solomon codes are the most commonly used variants of BCH codes. They have applications in a variety of communication systems: space communication links, digital subscriber loops, wireless systems, networking communications, and magnetic and data storage systems. Continual demand for ever higher data rates and storage capacity provide an incentive to devise very high-speed and space-efficient VLSI implementations of BCH decoders. The first decoding algorithm for binary BCH codes was devised by Peterson in 1960. Since then, Peterson's algorithm has been refined by Gorenstein and Zierler, Berlekamp, Massey, Chien, Forney, and many others.

BCH codes are generally developed as follows. GF(q) is defined as a finite field of q elements, q=2^(s), called the base field, and α is defined as a primitive element of extension field GF(q^(m)), where n|q^(m)−1. The variable t is defined as an error detecting BCH code of length n over GF(q) as the set of all sequences (c₀, c₁, . . . , c_(n-1)), c_(i)εGF(q) such that polynomial c(x)=c ₀ +c ₁ x+ . . . +c _(n-1) x ^(n-1) εGF(q ^(m))[x]

has roots in points: α¹, α², . . . , α^(2t). The BCH code with m=1 is called the Reed Solomon code, and the BCH code with s=1 is called the binary BCH code.

Encoding of BCH Codes

First, we calculate the generator polynomial g(x)εGF(q): g(x)=(x−α)(x−α ²) . . . (x−α ^(2t))=LCM{M ₁(x), M ₂(x), . . . , M _(2t)(x)},

where LCM is the least common multiplier and M_(i)(x) is the minimal polynomial for α^(i). Let (d₀, d₁, . . . , d_(k-1)) denote k data symbols that are to be transmitted over a communication channel, and d(x)=d₀+d₁x+ . . . d_(k-1)x^(k-1)εGF(q)[x]. The systematic encoding of vector (d₀, d₁, . . . , d_(k-1)) into a codeword (c₀, c₁, . . . , c_(n-1)) is as follows: c(x)=x ^(n-p) d(x)+t(x),

where p=deg g(x) and t(x)=−x^(n-p)d(x)mod g(x), c(x)=c₀+c₁x+ . . . +C_(n-1)x^(n-1).

Decoding of BCH Codes

There are many BCH decoder architectures. A typical BCH decoder works as follows. Let (c₀, c₁, . . . , C_(n-1)) be a transmitted codeword and (e₀, e₁, . . . , e_(n-1)) be an error vector in a communication channel, where in r (with r≦t) positions i₁, i₂, . . . , i_(r) there are non-zero values Y₁=e_(i) ₁ , . . . , Yr=e_(i) _(r) . Let also X₁=α^(i) ¹ , . . . , X_(r)=α^(i). Define e(x)=e₀+e₁x+ . . . +e_(n-1)x^(n-1) and t(x)=c(x)+e(x), t(x)=t₀+t₁x+ . . . +t_(n-1)x^(n-1), where (t₀, t₁, . . . , t_(n-1)) is a word is to be decoded. Then, the decoding algorithm consists of three main steps:

1. Syndrome Computation Block

The decoder begins by computing 2t syndrome values S ₀ =c(α), S ₁ =c(α²), . . . , S _(2t-1) =c(α^(2t)) 2. Key Equation Solver Block

This block is perhaps the most intricate part of BCH decoder. Define the syndrome polynomial S(x), error locator polynomial Λ(x), and error evaluator polynomial Ω(x) as follows:

${{S(x)} = {S_{0} + {S_{1}x} + \ldots + {S_{{2t} - 1}x^{{2t} - 1}}}},{{\Lambda(x)} = {{\Lambda_{0} + {\Lambda_{1}x} + \ldots + {\Lambda_{r}x^{r}}} = {\sum\limits_{i = 1}^{r}\left( {1 - {X_{i}x}} \right)}}},{{\Omega(x)} = {{\Omega_{0} + {\Omega_{1}x} + \ldots + {\Omega_{r - 1}x^{r - 1}}} = {\sum\limits_{i = 1}^{r}{Y_{i}X_{i}{\prod\limits_{{j = 1},{j \neq i}}^{r}\left( {1 - {X_{j}x}} \right)}}}}}$

It is well known that these three polynomials are related with the following key equation: Λ(x)S(x)=Ω(x)mod x ^(2t)

There are two major methods for solving the key equation: first, the Berlekamp-Massey algorithm (BM), and second, the extended Euclidean algorithm (eE). Until recently the architectures based on the eE algorithm were more popular because of its simplicity and regularity. In addition, they had smaller critical path delays then architectures based on the BM algorithm. Lately, however, BM based architectures have gained in popularity, due to a number of modifications in the standard BM algorithm that have made them even faster and more space-efficient than the eE based architectures.

3. Chien/Forney Block

The last block finds the positions of the errors, and corrects the errors using the Forney formula:

For  all  i ∈ {0, 1, …  , n − 1}: if  Λ(α^(−i)) = 0 ${{then}\mspace{14mu} t_{i}}:={t_{i} + \frac{\Omega\left( \alpha^{- i} \right)}{\Lambda^{\prime}\left( \alpha^{- i} \right)}}$ else  we  don′t  change  t_(i).

What is desired is a scalable architecture for the BM algorithm.

SUMMARY

The above and other needs are met by an improvement to a key equation solver block for a BCH decoder, where the key equation solver block having a number of multiplier units specified by X, where: t*(7*t−1)/(codeword_len−3)≦X<(t+1),

where t is a number of transmission errors for the key equation solver block to correct, and codeword_len is a length of a transmitted codeword to be decoded by the BCH decoder.

BRIEF DESCRIPTION OF THE DRAWINGS

Further advantages of the invention are apparent by reference to the detailed description when considered in conjunction with the figures, which are not to scale so as to more clearly show the details, wherein like reference numbers indicate like elements throughout the several views, and wherein:

FIG. 1 is a functional block diagram of a key equation solver block according to one embodiment of the present invention.

FIGS. 2-8 depict additional detail for the functional units depicted in FIG. 1, according to one embodiment of the present invention.

DETAILED DESCRIPTION

Multiplication in Galois fields is one of the most expensive operations in terms of the design area that is occupies on integrated circuits. For this reason, reducing the number of multipliers generally leads to a significant decrease in the amount of design area required.

In the embodiments of the key equation solver (KES) block according to the present invention, the number of clock cycles of service of one codeword depends on the number of multipliers, according to the following relationship: N=t*(7*t−1)/mult_num+3, where N is the number of clock cycles of service of one codeword, t is the number of errors to be corrected, and mult_num is the number of multipliers in the KES block. Hence, when the number of multipliers is reduced, the number of clock cycles generally increases.

For a pipeline decoder according to the present invention, the number of clock cycles of service for one codeword by the KES block is preferably no greater than the codeword length. As a result, the formula for the minimal acceptable number of multipliers for the pipeline decoder can be obtained as: min_mult_num=t*(7*t−1)/(codeword_len−3), where min_mult_num is the minimal acceptable number of multipliers for the pipeline decoder, t is the number of errors to correct, and codeword_len is the codeword length.

In a standard KES block, usually 2t or (t+1) multipliers are used. In the KES blocks according to the present invention, any number of multipliers can be used. The architecture of KES blocks according to the present invention preferably has a variable number of multipliers that is dependent, at least in part, on codeword lengths.

Key Equation Solver Block with Variable Number of Multipliers

The key equation solver block proposed herein is termed an inversionless Berlekamp-Massey algorithm (iBM). The embodiment of the key equation solver block described in this section depends on two parameters. First, parameter t is the number of errors to correct. If the number of errors to correct is more than or equal to t, then the key equation solver block returns a fail code. The second parameter k defines the number of multipliers. The number of multipliers is equal to n=]t/k[. Here ]x[ is a minimal integer number such that ]x[≧x. The inputs of the key equation solver block are 2t syndrome values: S₀, S₁, . . . , S_(2t-1). The output of the key equation solver block are t coefficients of the error locator polynomial: Λ₀, Λ₁, . . . , Λ_(t-1), and t−1 coefficients of the error evaluator polynomial: Ω₀, Ω₁, . . . , Ω_(t-2).

DEFINITIONS

If R is a register then RD is the data input to the register, RE is the enable input to the register, and RQ is the output of the register. If for the r clock cycle RD=A and RE=1, then for the r+1 clock cycle RQ=A. If for the r clock cycle RD=A, RQ=B, and RE=0, then for the r+1 clock cycle RQ=B. Denote by ⊕ and · sum and multiplication operations in the finite field, respectively.

Structure

The key equation solver block according to the embodiment described in this section uses the following registers:

1) SR₀, SR₁, . . . , SR_(2t-1) to save syndrome values,

2) Λ₀, Λ₁, . . . , Λ_(t-1) to save coefficients of the error locator polynomial,

3) L to save the degree of the error locator polynomial,

4) r to save the step index,

5) Ξ₀, Ξ₁, . . . , Ξ_(t-1),

6) Γ₀, Γ₁, . . . , Γ_(t-1),

7) Δ_(pr),

8) Δ, and

9) δ

Initialization

The key equation solver block according to this embodiment is initiated with the following values:

1) SR₀.D=S₀, SR₁.D=S₁, . . . , SR_(t-1).D=S_(t-1);

1) Λ₀.D=1, Λ₁.D=0, . . . , Λ_(t-1).D=0;

2) Γ₀.D=1, Γ₁.D=0, . . . , Γ_(t-1).D=0;

3) Δpr=1;

3) L=0; and

4) r=0.

Process

The key equation solver block according to this embodiment consists of two main steps:

1) Computation of the coefficients of the error locator polynomial; and

2) Computation of the coefficients of the error evaluator polynomial.

The computation of the coefficients of the error locator polynomial consists of 2t elementary steps. The q^(th) elementary step consists of 3k clock cycles:

${\left. 1 \right)\mspace{14mu}{\Delta.D}} = {{\overset{n - 1}{\underset{j = 0}{\oplus}}{{{\Lambda_{j}.Q} \cdot {{SR}_{r}._{Q - j}} \cdot Q}\mspace{14mu}\left( {{{remember}\mspace{14mu} n} =} \right\rbrack{t/{{k\left\lbrack {{is}\mspace{14mu}{the}\mspace{14mu}{number}\text{}\mspace{34mu}{of}\mspace{14mu}{multipliers}} \right)}.2}}\text{)}\mspace{14mu}{\Delta.D}}} = {{\Delta.Q} \oplus {\overset{{2n} - 1}{\underset{j = n}{\oplus}}{{\Lambda_{j}.Q} \cdot {{SR}_{r}._{Q - j}.Q.\ldots}}}}}$ ${k\text{)}\mspace{14mu}{\Delta.D}} = {{{\Delta.Q} \oplus {\overset{t - 1}{\underset{j = {n{({k - 1})}}}{\oplus}}{{\Lambda_{j}.D} \cdot {{SR}_{r}._{Q - j}.D.k}}}} + {1\text{)}\mspace{14mu}{Define}\mspace{14mu}\delta\text{:}}}$      if  Δ.Q ≠ 0  and  2L.Q ≤ r.Q      then  δ.D = 1      else  δ.D = 0;      Ξ_(j).D = Δ_(pr).Q ⋅ Λ_(j).Q; j = 0, 1, …  , n − 1.k + 2)  Ξ_(j).D = Δ_(pr).Q ⋅ Λ_(j).Q; j = n, n + 1, …  , 2n − 1.…2k)  Ξ_(j).D = Δ_(pr).Q ⋅ Λ_(j.)Q, j = n(k − 1), n(k − 1) + 1, …  , t − 1.2k + 1)  if  δ.Q ≠ 0  then  Γ_(j).D = Λ_(j).Q;       Λ_(j).D = Ξ_(j).D ⊕ Δ.Q ⋅ Γ_(j − 1).Q; j = 0, 1, …  , n − 1. 3k − 1)  if  δ.Q ≠ 0  then  Γ_(j).D = Λ_(j).Q;       Λ_(j).D = Ξ_(j).D ⊕ Δ.Q ⋅ Γ_(j − 1).Q;       j = n(k − 2), n(k − 2) + 1, …  , n(k − 1) − 1. 3k)  Λ_(j).D = Ξ_(j).D ⊕ Δ.Q ⋅ Γ_(j − 1).Q,    j = n(k − 1), n(k − 1) + 1, …  , t − 1;    if  δ.Q ≠ 0    then  Γ_(j).D = Λ_(j).Q, j = n(k − 1), n(k − 1) + 1, …  , t − 1;    otherwise  Γ₀.D = 0, Γ_(j).D = Γ_(j − 1).Q, j = 1, 2, …  , t − 1;    if  δ.Q ≠ 0  then  L.D = r.Q + 1 − L.Q  and  Δ_(pr).D = Δ.Q.   If  after  2t  elementary  steps  L.Q ≥ t  then  the  key  equation    solver  block $\mspace{40mu}{{returns}\mspace{14mu} a\mspace{14mu}{``{fail}"}\mspace{14mu}{{indication}.}}$

The computation of the coefficients of the error evaluator polynomial consists of t−1 elementary steps.

The q^(th) elementary step consists of k clock cycles:

${\left. 1 \right)\mspace{14mu}{\Delta.D}} = {{\overset{n - 1}{\underset{j = 0}{\oplus}}{{{\Lambda_{j}.Q} \cdot {{SR}_{r}._{Q - j}.Q.2}}\text{)}\mspace{14mu}{\Delta.D}}} = {{\Delta.Q} \oplus {\overset{{2n} - 1}{\underset{j = n}{\oplus}}{{\Lambda_{j}.Q} \cdot {{SR}_{r}._{Q - j}.Q.\ldots}}}}}$ ${k - {1\text{)}\mspace{14mu}{\Delta.D}}} = {{{\Delta.Q} \oplus {\overset{{n{({k - 1})}} - 1}{\underset{j = {n{({k - 2})}}}{\oplus}}{{{\Lambda_{j}.Q} \cdot {{SR}_{r}._{Q - j}.D.k}}\text{)}\mspace{14mu}\Omega_{q}}}} = {{\Delta.Q} \oplus {\overset{t - 1}{\underset{j = {n{({k - 1})}}}{\oplus}}{{\Lambda_{j}.D} \cdot {{SR}_{r}._{Q - j}.D.}}}}}$ Key Equation Solver Block Description

If R is a register and RE is not assigned, then RE is assumed to be one.

Interface and Registers

Inputs

1. S₀, S₁, S_(2t-1) are syndrome values.

2. start is a start signal.

Outputs

1. Λ₀, Λ₁, Λ_(t-1) are coefficients of the error locator polynomial.

2. Ω₀, Ω₁, . . . , Ω_(t-2) are coefficients of the error evaluator polynomial.

3. finish is a finish signal.

4. fail is a fail signal.

Constants

1. n=]t/k[.

2. m=3*k.

3. l=t mod n.

4. if l=0 then q=], otherwise q=2.

Registers

1. SR₀, SR₁, . . . , SR_(2t-1) are syndrome registers.

2. Λ₀, Λ₁, . . . , Λ_(t-1), are registers for the error locator polynomial coefficients.

3. finish is the finish signal register.

4. fail is the fail signal register.

5. L is the register to save the degree of the error locator polynomial.

6. r is a register to save the step index.

7. Ξ₀, Ξ₁, . . . , Ξ_(t-1).

8. Γ₀, Γ₁, . . . , Γ_(t-1).

9. T₀, T₁, . . . , T_(m-1) are clock registers for the error locator polynomial calculation.

10. T₀′, T₁′, T_(k-1)′ are clock registers for the error evaluator polynomial calculation.

11. M₀, M₁, . . . , M_(n-1) are output registers for the multipliers.

12. Δ_(pr).

13. Δ

14. Δ₀.

15. start_omega.

16. calc_omega.

17. L_(r).

18. rδ.

19. after_start.

Internal Wires

1. A₀, A₁, . . . , A_(n-1); B₀, B₁, . . . , B_(n-1) are inputs for the multipliers.

2. LL₀, LL₁, . . . , LL_(t-1).

3. δ.

4. sum.

5. sum_control.

Computations

1.  T₀.D = start⋁ ⫬ finish.Q&MUX(calc_omega.Q,   T_(m − 1).Q, T_(k − 1).Q);   T_(k).D =  ⫬ start& ⫬ finish.Q&    ⫬ calc_omega.Q&T_(k − 1).Q;   T_(i).D =  ⫬ start& ⫬ finish.Q&T_(i − 1).Q,   i = 1, 2, …  , k − 1, k + 1, …  , m − 1;   T₀^(′).D =  ⫬ start_omega.Q& ⫬ finish.Q&T_(k − 1)^(′).Q;   T_(k − 2)^(′) = start_omega.Q⋁( ⫬ finish.Q&T_(k − 3)^(′).Q);   T_(i)^(′).D =  ⫬ start_omega.Q& ⫬ finish.Q&T_(i − 1)^(′).Q;   i = 1, 2, …  , k − 3, k − 1.2.  SR_(i)D = MUX(start, SR_(i + 1).Q, S_(i)),   SR_(i).E = start⋁T_(k − 1).Q, i = 0, 1, 1...1  , t;   SR_(i)D = MUX(start,  ⫬ start_omega.Q&SR_((i + 1)mod(2t)).Q, S_(i)),   SR_(i), E = start⋁T_(k − 1).Q⋁start_omega.Q, i = t + 1, …  , 2t − 1.3.  A_(i) = (T₀.Q&SR_((2t − i)mod(2t)).Q⋁T₁.Q&SR_((2t − n − i)).Q⋁…⋁   T_(k − 1).Q&SR_((2t − (k − 1)n − i)).Q)⋁(T_(k).Q⋁…⋁T_(2k − 1).Q)&Δ_(pr).Q⋁   (T_(2k).Q⋁…⋁T_(3k − 1).Q)&Δ.Q, i = 0, 1, …  , l − 1;   A_(i) = (T₀.Q&SR_((2t − i)mod(2t)).Q⋁T₁Q&SR_((2t − n − i)).Q⋁…⋁   T_(k − q).Q&SR_((2t − (k − q)n − i)).Q)⋁(T_(k).Q⋁…⋁T_(k − 1).Q)&Δ_(pr).Q⋁   (T_(2k).Q⋁…⋁T_(3k − 1).Q)&Δ.Q, i = l, l + 1, …  , n − 1.4.  B₀ = ((T₀.Q⋁T_(k).Q)&Λ₀⋁(T₁ ⋅ Q⋁T_(k + 1).Q)&Λ_(n)⋁...⋁   (T_(k − 1).Q⋁T_(2k − 1).Q)&Λ_((k − 1)n)))⋁(T_(2k + 1).Q&Γ_(n − 1).Q⋁T_(2k + 2).Q&   Γ_(2n − 1).Q⋁…⋁T_(3k − 1).Q&Γ_((k − 1)n − 1).Q);   B_(i) = ((T₀.Q⋁T_(k).Q)&Λ_(i)⋁(T₁.Q⋁T_(k − 1).Q)&Λ_(n + i)⋁…⋁   (T_(k − 1).Q⋁T_(2k − 1).Q)&Λ_((k − 1)n − 1)))⋁(T_(2k).Q&Γ_(i − 1).Q⋁T_(2k + 1).Q&   Γ_(n + i − 1).Q⋁…⋁T_(3k − 1).Q&Γ_((k − 1)n + i − 1).Q), i = 1, 2, …  , l − 1;   B_(i) = ((T₀.Q⋁T_(k).Q)&Λ_(i)⋁(T₁.Q⋁T_(k + 1).Q)&Λ_(n + i)⋁…⋁   (T_(k − q).Q⋁T_(2k − q).Q)&Λ_((k − q)n + i)))⋁(T_(2k).Q&Γ_(i − 1).Q⋁T_(2k + 1).Q&    Γ_(n + i − 1).Q⋁…⋁T_(3k − q).Q&Γ_((k − q)n + i − 1).Q,   i = max (1, l), …  , n − 1.5.  M_(i).D = A_(i) ⋅ B_(i), i = 0, 1, …  , n − 1. ${{6.\mspace{14mu}{sum}} = {{\overset{n - 1}{\underset{j = 0}{\oplus}}{{M_{i}.Q.7.}\mspace{14mu}{sum\_ control}}} = {{{{T_{0}.Q}\bigvee{T_{2}.Q}\bigvee\ldots\bigvee{T_{k}.Q.8.}}\mspace{14mu}{\Delta.D}} = {{sum} + \left( {{{\Delta.Q}\&}{sum\_ control}} \right)}}}};$    Δ E = T₁.Q⋁sum_control.9.  Δ₀.D = (Δ.Q ≠ 0); Δ₀.E = T_(k + 1).Q.10.  L_(r).D = (2L.Q ≤ r.Q)&T_(k − 1).Q.11.  δ = L_(r).Q&Δ₀.Q& ⫬ calc_omega.Q.12.  r δ.D = δ; r δ.E = T_(k + 2).Q.13.  Δ_(pr).D = (start&1)⋁Δ.Q;    Δ_(pr).E = start⋁(r δ.Q&T_(2k − 1).Q).14.  L.D =  ⫬ start&(r.Q + 1 − L.Q); L.E = start⋁δ.15.  Ξ_(i), D =  ⫬ start&M_(i mod n).Q, Ξ_(i).E = start⋁T_(k + 1 + i/n).Q,   i = 0, 1, …  , t − 1. 16.  Γ₀.D = (start&1)⋁(r δ.Q&Λ₀.Q)⋁(Δ.Q&calc_omega.Q);    Γ₀.E = start⋁MUX(r δ.Q, T_(m − 1).Q⋁T_(k − 1)^(′).Q, T_(2k + 1).Q);    Γ_(i).D =  ⫬ start&MUX(r δ.Q, Γ_(i − 1).Q, Λ_(i).Q),   Γ_(i).E = start⋁MUX(r δ.Q, T_(m − 1).Q⋁T_(k − 1)^(′).Q,   T_((2k + 1 + i/n)mod m).Q), i = 1, 2, …  , t − 1. 17.  LL_(i) = Ξ_(i).Q ⊕ M_(i mod n).Q, i = 0, 1, …  , t − 1.18.  Λ₀.D = MUX(start, LL₀, 1); Λ_(i).D =  ⫬ start&LL_(i),   i = 1, 2, …  , t − 1;   Λ_(i).E = start⋁T_((2k + 1 + i.n)).Q& ⫬ calc_omega.Q,   i = 0, 1, …  , t − 2;    after_start.D = start;    Λ_(t − 1).E = start⋁(T₀.Q& ⫬ calc_omega.Q& ⫬ after_start.Q).19.  fail.D = (L.Q ≤ t).20.  r.D =  ⫬ start& ⫬ start_omega.Q&(r.Q + 1);    r.E = start⋁T_(m − 1).Q⋁T_(k − 1)^(′).Q.21.  start_omega.D =  ⫬ start&(r.Q =  = 2 * t − 1)&T_(m − 2).Q.22.  calc_omega.D =  ⫬ start& ⫬ finish.Q&(start_omega.Q⋁   calc_omega.Q).23.  Ω_(i) = Γ_(t − 2 − i).Q, i = 0, 1, …  , t − 2.24.  finish.D = T_(k − 1)^(′).Q& ⫬ finish.Q&(r.Q =  = t − 1). Key Equation Solver Block Scheme

FIG. 1 shows the complete structure of the key equation solver block according to the embodiment of the invention described herein. As depicted in FIG. 1 (and in FIGS. 2-8 as applicable) syndromes are stored in the registers SR_(i). Block T (FIG. 2) contains the generator for the control sequence T_(i) that governs one iteration of the iBM algorithm. Blocks A_(i) and B_(i) (FIGS. 4 and 6 (and FIG. 5 for Block B₀) respectively) act as multiplexers, switching the inputs of the multiplier units to the proper values for the current clock cycle, as indicated by T_(i).

The outputs of the multiplier units are stored in the registers M_(i). The partial results of the calculation of the new value for the error locator polynomial are stored in blocks ACC_(i) (FIG. 3B). Coefficients for the error locator polynomial are collected in the array of registers Λ_(i), and the register array Γ_(i) is used to store the coefficients for the auxiliary correcting polynomial. Blocks ΛΛ_(i) (FIGS. 7A, 7B, and 7C) and ΓΓ_(i) (FIGS. 8A and 8B) manage the enable inputs and data inputs for Λ_(i) and Γ_(i) respectively, according to the state of the control sequence T_(i). Block Δ (FIG. 3C) is used for the iterative calculation of the value Δ. FIG. 3A depicts Block SA_(i).

Block C contains logic that manages the iteration counter r, the error locator polynomial degree L, etc, and calculates the values of the signals Δ_(pr), rδ, finish, fail, start_omega and calc_omega. The schematics for these modules, except for the module C, are depicted in FIGS. 2-8. The configuration of the module C follows directly from the description of its outputs in the computation scheme.

The foregoing description of preferred embodiments for this invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Obvious modifications or variations are possible in light of the above teachings. The embodiments are chosen and described in an effort to provide the best illustrations of the principles of the invention and its practical application, and to thereby enable one of ordinary skill in the art to utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated. All such modifications and variations are within the scope of the invention as determined by the appended claims when interpreted in accordance with the breadth to which they are fairly, legally, and equitably entitled. 

1. In a key equation solver block for a processor-based BCH decoder, the improvement comprising the key equation solver block having a number of multiplier units specified by X, where: t*(7*t−1)/(codeword_len−3)≦X<(t+1), where t is a non-zero number of transmission errors for the key equation solver block to correct using the processor, and codeword_len is a length, greater than 3, of a transmitted codeword to be decoded by the processor-based BCH decoder. 